In-House AI Chips: Gimmick or Ultimate Moat? (The Li Auto M100 Case)

As Li Auto's CTO Xie Yan aptly noted: just as no leading automaker in the ICE era would completely outsource their engine and chassis, underlying AI compute is the new "engine" of the smart vehicle era.

For OEMs, building custom silicon is no longer just a defence against soaring hardware costs; it is the ultimate battle to avoid homogenization and retain control over their "digital soul." For Tier 1s and silicon suppliers, as top automakers build tight closed loops from bare metal straight to the OS, the traditional "turnkey" black-box model is rapidly becoming obsolete.

After looking into the hardcore technical details of the M100 chip below, every industry stakeholder must urgently ask: Where is your irreplaceable value in this completely reconstructed software-hardware ecosystem?

Recently, during an industry exchange focusing on the underlying computing architecture of vehicles, Li Auto shared detailed insights into its in-house 5nm high-compute chip, the "Mach M100," covering everything from initial conception to its successful tape-out. The technical choices behind this automotive-grade chip warrant a deeper look.

Many are asking: With mature, top-tier chip suppliers readily available, is it a PR gimmick or a strategic necessity for automakers to directly take on this highly capital-intensive and risky endeavor?

Before exploring the commercial motivations behind developing custom silicon, let's first examine this unique chip from a technical perspective.

The M100: Stepping Outside Traditional Architectures

The M100 is a massive chip with 45 billion transistors, built on a 5nm process, featuring a 400 square millimeter die and 1280 TOPS of physical compute. However, its core differentiator is its departure from the traditional von Neumann architecture used by most CPUs and GPUs. Instead, it adopts an orchestratable Dataflow Architecture—a concept rarely seen in the automotive sector.

It differs from familiar general-purpose chips in several fundamental ways:

1. From "Instruction-Driven" to "Data-Driven": General-purpose architectures are instruction-driven, requiring massive instruction queues and schedulers. The M100 eliminates the central instruction queue, meaning computation is entirely data-triggered. Once data arrives, computation begins automatically, and the output from one process flows directly into the next.

2. Eliminating Hardware Cache to Reshape Data Flow: Traditional chips use complex hardware caches to mitigate data transfer latency. The M100 removes hardware cache logic entirely, utilizing SRAM exclusively. Its 56 homogeneous computing units are fully interconnected via a mesh bus, allowing intermediate results to flow point-to-point without repeatedly writing back to main memory.

3. Simplified Hardware, Shifted Complexity: By removing complex control circuits, the saved transistors are converted into raw computing power, enabling the M100 to achieve an 80% operational efficiency. The trade-off is that the immense scheduling complexity is shifted entirely to the software (compiler) level.

Why would an automaker go to such lengths to reconstruct underlying silicon logic? This stems primarily from two core considerations.

Core Motivation 1: Computing is Becoming the Second Largest Cost and is Soaring

The industry is facing a harsh reality: computing capability is already the second-largest cost component in a vehicle, trailing only the battery, and this trend is accelerating.

As vehicles evolve into "embodied AI," the demand for multi-modal and end-to-end models is exploding. In the future, per-vehicle computing costs are highly likely to climb from the current $2,000 to $4,000, $8,000, or even over $10,000. Without mastering underlying AI capabilities, automakers will face immense hardware cost pressures.

Furthermore, existing general-purpose chips (GPGPUs) face efficiency bottlenecks. To maintain versatility across various industries, GPGPUs waste significant compute on data transfer and scheduling during massive AI inference tasks, hitting a hard ceiling on actual utilization rates.

Core Motivation 2: Algorithms Will Converge; Full-Stack In-House Development is the Only Way to Build a Differentiation Moat

Not all automakers will choose to build their own chips. However, Li Auto’s decision to take this heavy and difficult technical path is driven by a clear first principle: seizing absolute control over the core capabilities of future smart vehicles.

As Li Auto CTO Xie Yan candidly noted during the exchange:

"If the core of a smart vehicle is its AI capability, then the underlying foundation of that capability must be mastered by the automaker itself. Just like in the ICE (Internal Combustion Engine) era, a truly leading automaker would never completely outsource core mechanical elements like the engine and chassis to suppliers. Otherwise, there would be no difference between Company A and Company B."

A consensus is gradually emerging in the industry: in the long run, the algorithmic ideas behind large AI models will inevitably converge. Relying solely on algorithms to build a long-term moat is becoming increasingly difficult. The future wall of differentiation will undoubtedly stem from "software-hardware integrated design."

We can see this in the vertical integration chart below. Built on top of the custom hardware (L1), layers L2 through L5 are completely self-developed software stacks, forming a deeply synergistic closed loop:

Layer	Core Component	Technical Highlights & Design Purpose
L5:Application Model Layer	Large Models	Runs the Mach VLA multi-modal model and end-to-end autonomous driving models, directly defining the terminal intelligence experience.
L4:Operating System Layer	Self-developed OS	Provides hardware-level isolation and virtualization; supports high-frequency concurrent task scheduling and cross-domain ECU integrated control.
L3:Core Compiler Layer	AI Compiler	Responsible for spatio-temporal joint optimization and automatic concurrent strategy solving, efficiently mapping models to the underlying hardware.
L2:Operator Implementation Layer	Operators	A highly efficient set of mathematical operators utilizing "operator fusion" technology to minimize invalid data transfers.
L1:Physical Hardware Layer	Architecture	M100 orchestratable Dataflow Architecture. Streamlines control logic and hardware cache to boost base compute utilization.

When the underlying hardware (L1) is streamlined to the extreme, the role of the compiler (L3) and operating system (L4) becomes paramount. By successfully navigating this rigorous Software-Hardware Co-design system, the automaker has managed to compress end-to-end latency down to an impressive 0.28 seconds.

Industry Implications and Observations

Before discussing broader industry impacts, one technical detail stands out: this 5nm, 45-billion-transistor chip achieved a successful tape-out on its very first try. For a company with no history of developing automotive-grade, high-compute chips, executing a novel architecture flawlessly on the first attempt indirectly validates their massive investment in software-hardware co-simulation and engineering execution.

However, the path to full-stack in-house development is agonizing. Building a chip tests organizational management as much as capital. Breaking down departmental silos so that hardware architects, compiler geeks, and traditional automotive engineers can collaborate via objective, quantitative data is a massive managerial hurdle for cross-disciplinary endeavors.

From an industry observer's perspective, controlling everything from the underlying hardware to top-tier software enables true cross-domain integration. This represents a strategic exploration by some companies to break free from homogeneous competition and secure core control over their products. As massive intelligent terminals, vehicles are actively participating in and forcing the innovation of next-generation computer architectures.

Faced with immense R&D costs and trial-and-error risks, an open question remains for the industry. In the coming years, will more top-tier automakers pursue this vertical integration of full-stack in-house silicon, or will a new "Joint-design" ecosystem emerge? How will this underlying shift reshape traditional automotive supply chains? To discuss what this means for your chip, software and supplier roadmap please get in touch: info@sbdautomotive.com  Andy Qiu, Senior Manager at SBD Automotive